Design and implementation of the hottest USB20 vir

2022-07-29
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Design and implementation of USB2.0 virtual logic analyzer

introduction

the traditional logic analyzer is bulky, expensive, and has limited number of channels, and there are many limitations in data collection, transmission, storage, display, etc., which greatly affect its application in practice. Using high-performance FPGA chip for data processing, making full use of the powerful processing function of PC and cooperating with the virtual logic analyzer developed by LabVIEW graphical language, its data processing and transmission rate are greatly improved, and its applicability is greatly enhanced. Its display, operation interface and low cost have great advantages and development prospects compared with the traditional logic analyzer

working principle

in this design, the cyclone series FPGA device EP1C3 of Altera company is selected for data acquisition and processing, and SRAM is connected externally for data storage. The system completes the communication with PC through the high-performance PIC MCU pic18f6620, receives the trigger and configuration information sent by PC, and controls the system to upload the collected and processed data to PC for display. The interface between MCU and PC is realized by using the interface chip CP2102 conforming to USB2.0 specification

first, PC sends trigger word information, data acquisition control information and start data acquisition signal to FPGA; MCU sends data to external DAC to generate threshold voltage; The collected input signal is compared with this threshold voltage through a high-speed comparator to ensure that although China's economic growth slows down as a whole, its value is 0 or 1. After receiving the start data acquisition signal sent by PC, FPGA collects data according to the set working mode, and the data of each channel is shifted and input into the internal cache of FPGA and stored in the external SRAM. FPGA compares the collected data stored in the cache with the set trigger word, trigger mode and mask bit. Once the trigger conditions are met, set the trigger flag and record the trigger position. When the data is collected to the set number of points, FPGA sends the acquisition completion signal to PC. After receiving this signal, the upper computer sends the data reading command, and the system reads back the collected data and displays it on the PC screen. The system function block diagram is shown in Figure 1

Figure 1 system function block diagram

system trigger module design

trigger module is the core part of the whole system, mainly including sampling clock selection module, trigger level setting and trigger circuit

sampling clock selection module

clock selection module is used to select sampling frequency. The optional clock sources include: external clock (provided by active crystal oscillator), PWM clock generated by PWM module of single chip microcomputer, external clock input (provided by additional equipment), and taking the nth channel digital signal input as the sampling clock

trigger level setting

trigger level is used to determine the high and low levels of the sampling signal correctly recognized by the system. The module consists of a serial digital to analog converter TLC5615 and a high-speed comparator lt1721. Before sampling, the MCU sends trigger level data to the DAC, and the converted level signal (range from 0~+5v) is sent to the high-speed comparator

trigger circuit

trigger circuit is used to judge whether the sampling signal meets the trigger conditions and generate trigger actions respectively. When the collected signal meets the trigger conditions set by the user, the system records the trigger position and generates a trigger signal to inform the upper computer to read and display the sampling data. The trigger circuit has three optional trigger modes: immediate trigger, sequential trigger and parallel trigger

immediate trigger

when the upper computer sends the immediate trigger word and start sampling instruction to FPGA, FPGA starts sampling and immediately generates trigger signal. The sampling circuit stores the collected signal in the external SRAM until the specified number of points is collected, and then stops sampling, and sends the sampling end signal to the upper computer to inform it to read the sampling data. The trigger point position read back in this mode is 0

sequential trigger

this method sets an 8-bit sequence trigger. The trigger signal is generated only when the signal of the tested channel meets the 8-bit sequence set by the trigger word in turn. At the same time, the shielding bit is added for the flexibility of operation. If it is insensitive to the data of a certain bit, the corresponding mask bit can be set to 0, and this bit will not be detected when judging the trigger condition

using the sequential trigger mode, you can select a sequence with a maximum length of 8 bits for any channel to trigger. During trigger setting, in addition to setting the trigger mode (selecting the size of the indenter and base loaded in sequence) and selecting the sampling frequency, channel selection, trigger word and shielding bit setting are also required. The Verilog HDL algorithm source program is as follows:

if (((dbuf^{trigword[1], trigword[0]}) &{enbit[1], enbit[0]}) = = 8'h00)

begin

trigflag=2'b01; Trigpoint[6:0]

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